Getting Started with RISC-V Tel Aviv

To stand out against the many available options, RISC-V processor core developers must thoroughly verify their designs. This requirement goes beyond Instruction Set Architecture (ISA) compliance checking to include optional ISA features, custom extensions, and microarchitectural implementation choices.

RISC-V system-on-chip (SoC) designers must be able to confirm the integrity of the RISC-V cores they integrate, including proof that no Trojans or hardware vulnerabilities lurk in the design, and verify that the cores are integrated properly into the SoC. Safety-critical applications with strict standards add even more verification requirements.

This talk presents a verification flow covering the full scope of integrity for RISC-V cores and SoCs, spanning functional correctness, safety, security, and trust. It is essential for RISC-V core developers, engineers evaluating cores for possible use, and SoC teams integrating RISC-V cores from internal or external sources.