Name: Verification and Customization of RISC-V Cores and SoCs - Larry Lapides, Imperas Software
Start: 2019-09-16T14:10:00+0300
End: 2019-09-16T14:30:00+0300

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Verification and Customization of RISC-V Cores and SoCs - Larry Lapides, Imperas Software

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This talk will outline the keys steps for RISC-V implementors to adapt and extend the base processor functionality with custom extensions and instructions.

Key areas of the design development are covered including compliance and verification in addition to the profiling and design of custom instructions. Also, using advanced techniques of cycle approximate timing with analysis tools, designers can tune the processor to optimize the performance for the next generation of processors for Domain-specific Applications.

Speakers

Larry Lapides

VP Sales & Marketing, Imperas Software

Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before... Read More →

Imperas RISC V Roadshow (Sept 10 2019) (1) pdf

Monday September 16, 2019 14:10 - 14:30 IDT
King David Hall

Presentation

Session Slides Included Yes

Getting Started with RISC-V Tel Aviv

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Larry Lapides