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Getting Started with RISC-V Tel Aviv
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Monday
, September 16
09:30 IDT
Introduction to RISC-V - Calista Redmond, RISC-V Foundation
King David Hall
09:50 IDT
Rocinante: Motor Control SoC with Integrated RISC-V Core - Dr. Onno Martens, Trinamic Motion Control
King David Hall
10:10 IDT
Embedded Software Development for RISC-V Based SoC - Eyck Jentzsch, Minres Technology GmbH
King David Hall
11:00 IDT
SCRx Family of the RISC-V Compatible Processor IP by Syntacore - Alexander Redkin & Pavel Khabarov, Syntacore
King David Hall
11:20 IDT
RISC-V SoC FPGA Brings Real-Time to Linux - Peter Trott, Microchip Technology
King David Hall
11:40 IDT
Machine Learning on Battery Operated Devices at the Very Edge Using a Multi-core RISC-V Based Processor - Martin Croome, GreenWaves
King David Hall
13:10 IDT
Fast Start into RISC-V for AIoT with A+ Core - Morris Hung, Andes Technology
King David Hall
13:30 IDT
SweRV Core & CHIPS Alliance Initiatives - Ted Marena, Western Digital
King David Hall
13:50 IDT
Verifying the Full Scope of RISC-V Integrity - Nicolae Tusinschi, OneSpin
King David Hall
14:10 IDT
Verification and Customization of RISC-V Cores and SoCs - Larry Lapides, Imperas Software
King David Hall
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Getting Started with RISC-V Tel Aviv
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King David Hall
King David Hall Foyer (Grill Room)
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Monday
, September 16
Venue
King David Hall
King David Hall Foyer (Grill Room)
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